Single event upset reinforcement technology of DICE flip-flop based on layout design

基于版图设计的DICE触发器单粒子翻转加固技术

¹ School of Computer Science, Northwestern Polytechnical University, Xi'an 710072, China
² Xi'an Institute of Space Radio Technology, Xi'an 710199, China

Received: 17 March 2022

Abstract

D flip-flop is the basis of timing logic circuit, and SEMU phenomenon tends to be serious with the integrated circuit process size shrinking to nanometer scale. The anti-SEU ability based on DICE structure for D flip-flop cannot meet the requirements of aerospace engineering. Based on the SEU reinforcement technology of D flip-flop under nano-technology and the SEU mechanism of DICE structure, a layout-level anti-SEU flip-flop design method based on DICE circuit structure is proposed considering the circuit performance, area, power consumption and other resource costs. And then a D flip-flop with SEU resistance is designed by commercial 65 nm process, and the designed flip-flop area is 1.8 times that of commercial structure flip-flop. The function and and radiation simulation results indicate that the establishment time and transmission delay of the flip-flop are equivalent to those of the commercial one, and no SEU occurs under the Ge ion bombardment with the LET threshold of approximately 37 MeV·cm²/mg. The performance of the flip-flop circuit and the ability to resist single particle soft error are excellent. In the anti-radiation ASIC design, the area, wiring resources and timing overhead caused by the reinforcement of the D flip-flop circuit are greatly saved.

摘要

D触发器是时序逻辑电路的基础, 随着集成电路工艺尺寸进入纳米级, 单粒子多节点翻转(single event multiple upset, SEMU)现象趋于严重, 双互锁存单元(dual interlocked storage cell, DICE)触发器加固设计方法的抗单粒子翻转(single event upset, SEU)能力已不能满足宇航需求。基于纳米工艺下D触发器的SEU加固技术以及DICE结构的翻转机理, 兼顾电路性能、面积和功耗等资源开销, 提出了一种以DICE电路结构为基础的版图级抗SEU触发器设计方法, 并采用商用65 nm工艺实现了一款抗SEU的D触发器设计, 其面积仅为商用结构触发器的1.8倍。电路功能及辐照性能仿真表明, 该触发器的建立时间和传输延迟与商用结构触发器相当, 在线性传输能(linear energy transfer, LET)阈值大约为37 MeV·cm²/mg的Ge离子轰击下没有发生SEU, 触发器电路的性能和抗单粒子软错误能力表现优秀。在抗辐照专用集成电路设计中, 极大节省了由加固D触发器电路所带来的面积、布线资源和时序开销。