Hardware security and reliability verification based on fault propagation model

基于故障传播模型的硬件安全性与可靠性验证方法

¹ Beijing Smart-Chip Microelectronics Technology Co., Ltd., Beijing 100000, China
² Shenzhen Research Institute of Northwestern Polytechnical University, Shenzhen 518057, China

Received: 14 February 2023

Abstract

Large scale integrate circuits is facing serious threat such as design vulnerabilities, side channels, and hardware Trojans. Traditional functional verification method is difficult to ensure high test coverage, and it is also difficult to detect security vulnerabilities such as side channels and stealthy hardware Trojans. Formal verification methods focus on the equivalence and functional correctness of design, and are difficult to meet security and reliability verification needs. The present work proposes a hardware security and reliability verification method from formal model. The present method can develop formal models for describing the security and reliability behaviour of hardware designs. It can detect potential security vulnerabilities in hardware designs. Experimental results show that the verification method is effective in detecting sensitive information leakage and modification caused by side channels and hardware Trojans.

摘要

大规模集成电路正面临着诸如设计脆弱性、侧信道、硬件木马等安全漏洞的威胁。传统的功能测试验证方法无法遍历所有的输入空间, 同样无法检测侧信道安全漏洞。现有的形式化验证方法关注硬件设计的等价性和功能的正确性, 难以满足安全性和可靠性验证需求。研究面向安全性和可靠性验证的形式化模型, 形成有效的硬件安全性与可靠性形式化验证方法。该方法能够从门级对集成电路进行建模, 生成细粒度的形式化模型, 实现对安全性与可靠性的形式化验证, 可以捕捉硬件设计中潜在的安全隐患。实验结果表明该验证方法对硬件设计中存在的侧信道和硬件木马导致的信息泄露和篡改有很好的检测效果。