Open Access
 Issue JNWPU Volume 42, Number 1, February 2024 92 - 97 https://doi.org/10.1051/jnwpu/20244210092 29 March 2024

This is an Open Access article distributed under the terms of the Creative Commons Attribution License (https://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

## 1 故障效应传播模型

### 1.2 数字电路的故障效应传播模型

 图1数字电路故障效应传播模型

## 2 硬件安全性与可靠性验证方法

set USB=high

assert PC=low

set G=high

assert MEM=low

### 2.2 安全性与可靠性验证

Design Compiler是一款电路综合的核心工具, 用于将HDL描述的RTL级电路转换成门级网表。Questa Formal是一款基于断言的形式化验证工具, 内置SAT(boolean satisfiability problem)求解器, 用于验证是否存在违背安全约束的电路设计。

set G_t high

set default_value_t low

assert output_t low

 图2硬件安全性与可靠性验证方案

## 3 实验与分析

 图3实验流程

### 3.2 时间侧信道检测

set inExp_t=32′hFFFFFFFF

set default_label=0

 图4RSA密码算法核硬件结构
 图5时间侧信道检测的反例波形

### 3.3 X-传播验证

assume ＄all_input_label=0

assume ＄default_init_value=1

assert cypher_t==32′h0

 图6X-传播验证的反例波形

### 3.4 硬件木马检测

BasicRSA-T100硬件结构如图 7所示。

assume inExp_t=32′hFFFFFFFD

assume ＄default_label=0

 图7BasicRSA-T100硬件结构图
 图8硬件木马验证的反例波形

## References

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## All Figures

 图1数字电路故障效应传播模型 In the text
 图2硬件安全性与可靠性验证方案 In the text
 图3实验流程 In the text
 图4RSA密码算法核硬件结构 In the text
 图5时间侧信道检测的反例波形 In the text
 图6X-传播验证的反例波形 In the text
 图7BasicRSA-T100硬件结构图 In the text
 图8硬件木马验证的反例波形 In the text

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