Open Access
Issue
JNWPU
Volume 42, Number 3, June 2024
Page(s) 506 - 513
DOI https://doi.org/10.1051/jnwpu/20244230506
Published online 01 October 2024
  1. MAO Baolei, MU Dejun, HU Wei, et al. Quantitative analysis of sliding windows attack for the RSA timing channel[J]. Journal of Xidian University, 2017, 44(5): 115–120. [Article] (in Chinese) [Google Scholar]
  2. HU W, WU L, TAI Y, et al. A unified formal model for proving security and reliability properties[C]//2020 IEEE 29th Asian Test Symposium, 2020: 1–6 [Google Scholar]
  3. HU W, MAO B, OBERG J, et al. Detecting hardware trojans with gate-level information-flow tracking[J]. Computer, 2016, 49(8): 44–52. [Article] [CrossRef] [Google Scholar]
  4. ZHANG Q, HE J, ZHAO Y, et al. A formal framework for gate-level information leakage using z3[C]//2020 Asian Hardware Oriented Security and Trust Symposium, 2020: 1–6 [Google Scholar]
  5. ZHANG D, WANG Y, SUH G E, et al. A hardware design language for timing-sensitive information-flow security[J]. ACM Sigplan Notices, 2015, 50(4): 503–516. [Article] [Google Scholar]
  6. BIDMESHKI M M, MAKRIS Y. VeriCoq: a Verilog-to-Coq converter for proof-carrying hardware automation[C]//2015 IEEE International Symposium on Circuits and Systems, 2015: 29–32 [Google Scholar]
  7. HU W, ARDESHIRICHAM A, KASTNER R. Hardware information flow tracking[J]. ACM Computing Surveys, 2021, 54(4): 1–39 [Google Scholar]
  8. ARDESHIRICHAM A, HU W, KASTNER R. Clepsydra: modeling timing flows in hardware designs[C]//2017 IEEE/ACM International Conference on Computer-Aided Design, 2017: 147–154 [Google Scholar]
  9. ARDESHIRICHAM A, HU W, MARXEN J, et al. Register transfer level information flow tracking for provably secure hardware design[C]//Design, Automation & Test in Europe Conference & Exhibition, 2017: 1691–1696 [Google Scholar]
  10. GUO X, DUTTA R G, HE J, et al. QIF-Verilog: quantitative information-flow based hardware description languages for pre-silicon security assessment[C]//2019 IEEE International Symposium on Hardware Oriented Security and Trust, 2019: 91–100 [Google Scholar]
  11. JIN Y, MAKRIS Y. Proof carrying-based information flow tracking for data secrecy protection and hardware trust[C]//2012 IEEE 30th VLSI Test Symposium, 2012: 252–257 [Google Scholar]
  12. SHAKYA B, HE T, SALMANI H, et al. Benchmarking of hardware trojans and maliciously affected circuits[J]. Journal of Hardware and Systems Security, 2017(1): 85–102 [CrossRef] [Google Scholar]

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