Design of High Speed and Precision and Low-Power LVDS Driver for CMOS Image Sensor

一种用于CMOS图像传感器的高速高精度低功耗LVDS驱动器设计

¹ Xi'an Microelectronic Technology Institute, Xi'an 710065, China
² School of Microelectronics, Xi dian University, Xi'an 710065, China

Received: 28 May 2019

Abstract

Aiming at the requirement of high speed and precision, low-power and large-capacity load of serial data interface for aerospace super large array(15k×15k) CMOS image sensor, a design scheme low voltage differential signal (LVDS) driver by combining the split-length method with the pre-emphasis technique is proposed. Firstly, comparing with the general design schemes, the present scheme uses the split-length compensation method to increase effectively the unity-gain bandwidth while keeping the op-amp gain constant. Secondly, the pre-emphasis technique is used to compensate the LVDS driver for high-frequency components to improve the driving capability of the capacitive load and high speed signal integrity (SI). The simulation results show that the accuracy of the common-mode feedback voltage is improved by using the split-length compensation method, and also the common-mode voltage changes below 15 mV. The pre-emphasis technique is used to enhance the amplitude of the high-frequency components lost during the high-speed transmission. The quality of the signal eye diagram during high-speed transmission reduces the bit error rate, and both the transmission rate and the driving load capacity are two times more than the general design (1.2 Gb/s@12 pF), and the quiescent current consumption is only 4.6 mA@12 pF. The present LVDS driver design is implemented in a typical CMOS process of 0.18 μm.

摘要

针对宇航超大面阵(15k×15k)CMOS图像传感器中读出链路后级对串行数据接口高速、高精度、低功耗以及驱动大容性负载的需求，提出了一种基于沟道长度分割的方法和预加重技术相结合的低压差分信号(low voltage differential signal，LVDS)驱动器设计方案。与常见设计方案相比，该方案采用沟道长度分割补偿方法在兼顾运放增益的同时，有效提高单位增益带宽；其次采用预加重技术对LVDS驱动器进行高频分量补偿，提高大容性负载驱动能力和高速信号完整性。仿真结果表明：基于沟道长度分割补偿法有效提高了共模反馈电压信号的精度，仿真验证了实际共模电压信号变化小于15 mV；采用预加重技术对高速传输过程中损失的高频分量进行幅度增强，有效改善了高速数据传输过程中信号眼图质量，同时传输速率和驱动负载能力均提升2倍以上(1.2 Gb/s@12 pF)，静态电流消耗仅为4.6 mA@12 pF，所提出的LVDS驱动器设计方案采用典型0.18 μm CMOS工艺设计实现。