Volume 39, Number 1, February 2021
|Page(s)||126 - 134|
|Published online||09 April 2021|
On-chip data organization and access strategy for spaceborne SAR real-time imaging processor
School of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an 710072, China
2 Engineering Research Center of Embedded System Integration, Xi'an 710072, China
3 National Engineering Laboratory for Integrated Aero-Space-Ground-Ocean Big Data Application Technology, Xi'an 710072, China
Spaceborne SAR(synthetic aperture radar) imaging requires real-time processing of enormous amount of input data with limited power consumption. Designing advanced heterogeneous array processors is an effective way to meet the requirements of power constraints and real-time processing of application systems. To design an efficient SAR imaging processor, the on-chip data organization structure and access strategy are of critical importance. Taking the typical SAR imaging algorithm-chirp scaling algorithm-as the targeted algorithm, this paper analyzes the characteristics of each calculation stage engaged in the SAR imaging process, and extracts the data flow model of SAR imaging, and proposes a storage strategy of cross-region cross-placement and data sorting synchronization execution to ensure FFT/IFFT calculation pipelining parallel operation. The memory wall problem can be alleviated through on-chip multi-level data buffer structure, ensuring the sufficient data providing of the imaging calculation pipeline. Based on this memory organization and access strategy, the SAR imaging pipeline process that effectively supports FFT/IFFT and phase compensation operations is therefore optimized. The processor based on this storage strategy can realize the throughput of up to 115.2 GOPS, and the energy efficiency of up to 254 GOPS/W can be achieved by implementing 65 nm technology. Compared with conventional CPU+GPU acceleration solutions, the performance to power consumption ratio is increased by 63.4 times. The proposed architecture can not only improve the real-time performance, but also reduces the design complexity of the SAR imaging system, which facilitates excellent performance in tailoring and scalability, satisfying the practical needs of different SAR imaging platforms.
星载SAR成像需对大量输入数据进行实时成像处理，且功耗受限，设计高效率异构阵列处理器是满足功耗约束和实时性要求的有效方法，而片上数据组织结构和访问策略是设计的关键。在分析典型的CSA（chirp scaling algorithm）SAR成像算法的基础上，提取了SAR成像的数据流模型。提出了一种跨区域交叉放置和数据排序同步访问的存储策略，通过片上多级数据缓存结构，有效缓解存储带宽问题，支持FFT/IFFT和相位补偿操作的流水处理，确保成像计算高效执行。基于该存储策略的处理器可实现高达115.2 GOPS的吞吐量，采用65 nm技术可实现高达254 GOPS/W的能效。与CPU+GPU加速方案相比，性能/功耗比提高了63.4倍。该结构提高了实时性能，降低系统设计的复杂度，具有良好的可扩展性，可满足不同SAR成像平台的需求。
Key words: heterogeneous array / SAR imaging / data sort / cross-placement / high throughput / scalability / on-chip data organization / access strategy
关键字 : 异构阵列 / SAR成像 / 数据排序 / 交叉放置 / 高吞吐量 / 可扩展
© 2021 Journal of Northwestern Polytechnical University. All rights reserved.
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