Volume 37, Number 3, June 2019
|Page(s)||515 - 522|
|Published online||20 September 2019|
Memory Compact High-Speed QC-LDPC Decoder Based on FPGA
School of Electronics and Information, Northwestern Polytechnical University, Xi’an, 710072, China
2 China Academy of Space Technology, Xi’an, 710010, China
In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.
提出了一种高速部分并行准循环低密度奇偶校验码（quasi-cyclic low density parity check codes，QC-LDPC）译码器架构和该架构下的2种紧缩性存储策略，采用将多个相邻行的硬判决码字和外信息压缩到一个存储单元、硬判决待输出码字信息紧缩性存储及相对应的高速译码器架构，不仅减少了用于硬判决码字的存储块的数量，而且可以便于一个时钟周期内对多个数据同时进行访问并处理，从而提高了译码器的数据处理吞吐量。通过采用Xilinx XC4VLX160 FPGA实现CCSDS标准中的LDPC译码器验证了文中提出的这种紧缩性存储策略及其高速译码器架构可以有效地利用FPGA资源来实现高速译码器，实现结果显示该译码器在布局布线后时钟频率可以工作在250 MHz，译码器采用14次迭代，对应2 Gb/s的译码吞吐量。
Key words: quasi-cyclic low density parity check codes (QC-LDPC) / LDPC decoder / BRAM memory / FPGA / CCSDS / hard decisions / throughput
关键字 : QC-LDPC码 / LDPC译码器 / BRAM存储器 / FPGA / CCSDS
© 2019 Journal of Northwestern Polytechnical University. All rights reserved.
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